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Karlsruhe Institut of Technology

Young Investigator Network
YIN-Office

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76131 Karlsruhe

Tel. +49 721 608-46184

E-Mail: infoXad7∂yin kit edu

Das KIT ist seit 2010 als familiengerechte Hochschule zertifiziert.
Dr. Lars Bauer

Dr. Lars Bauer

[sci.] Gruppenleiter am Lehrstuhl für eingebettete Systeme
Informatik
eingebettete Systeme

Gruppe: [prev.] YIG
Raum: Deutschland, KIT
Tel.: +49 721 608-44218
lars bauerByd8∂kit edu


Institut für Technische Informatik

Lehrstuhl für Eingebettete Systeme

Campus Süd

Haid-und-Neu-Str. 9

76137 Karlsruhe



Ausgewählte Publikationen

 

Books

  • L. Bauer, J. Henkel, “Run-time Adaptation for Reconfigurable Embedded Processors”, Springer Science+Business Media, LLC, 2011, ISBN 978-1-4419-7411-2, e-ISBN 978-1-4419-7412-9, DOI 10.1007/978-1-4419-7412-9.

 

 

Journals/Magazines

  • M. Shafique, L. Bauer, J. Henkel, “Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms”, Journal of Signal Processing Systems (JSPS’10), Special Issue: Embedded Multimedia Systems, Volume 60, Issue 2, pp. 183-210, August 2010.
  • L. Bauer, M. Shafique, J. Henkel, “Efficient Resource Utilization for an Extensible Processor through Dynamic Instruction Set Adaptation”, IEEE Transaction on Very Large Scale Integration (TVLSI’08), Special Section on Application-Specific Processors, Volume 16, Issue 10, pp. 1295-1308, October 2008.

 

 

Conferences/Symposia

  • S. Kobbe, L. Bauer, J. Henkel, D. Lohmann, W. Schröder-Preikschat: “DistRM: Distributed Resource Management for On-Chip Many-Core Systems”, IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS’11) Taipei, Taiwan, October 2011 (accepted for publication).
  • W. Ahmed, M. Shafique, L. Bauer, J. Henkel: “Adaptive Resource Management for Simultaneous Multitasking in Mixed-Grained Reconfigurable Multi-core Processors”, IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS’11), Taipei, Taiwan, October 2011 (accepted for publication).
  • J. Henkel, L. Bauer, M. Hübner, A. Grudnitsky: “i-Core: A run-time adaptive processor for embedded multi-core systems”, International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA’11), Las Vegas, Nevada, USA, July 2011 (invited paper, accepted for publication).
  • L. Bauer, M. Shafique, J. Henkel, “Concepts, Architectures, and Run-time Systems for Efficient and Adaptive Reconfigurable Processors”, NASA/ESA 6th Conference on Adaptive Hardware and Systems (AHS’11), San Diego, CA, USA, June 2011 (invited paper).
    Received the
    MaXentric Technologies AHS’11 Best Paper Award.
  • W. Ahmed, M. Shafique, L. Bauer, M. Hammerich, J. Henkel, J. Becker, “Run-Time Resource Allocation for Simultaneous Multi-Tasking in Multi-Core Reconfigurable Processors”, IEEE 19th Symposium on Field-Programmable Custom Computing Machines (FCCM’11), Salt Lake City, Utah, USA, pp. 29-32, May 2011.
  • M. Shafique, L. Bauer, W. Ahmed, J. Henkel, “Minority-Game-based Resource Allocation for Run-Time Reconfigurable Multi-Core Processors”, IEEE/ACM 14th Design Automation and Test in Europe Conference (DATE’11), Grenoble, France, pp. 1261-1266, March 2011.
  • W. Ahmed, M. Shafique, L. Bauer, J. Henkel, “mRTS: Run-Time System for Reconfigurable Processors with Multi-Grained Instruction-Set Extensions”, IEEE/ACM 14th Design Automation and Test in Europe Conference (DATE’11), Grenoble, France, pp. 1554-1559, March 2011.
  • M. Shafique, L. Bauer, J. Henkel, “Selective Instruction Set Muting for Energy-Aware Adaptive Processors”, IEEE/ACM 28th International Conference on Computer-Aided Design (ICCAD’10), San Jose, CA, USA, pp. 353-360, November 2010.
    Nominated as IEEE/ACM William J. McCalla ICCAD’10 Best Paper Candidate.
  • R. Koenig, L. Bauer, T. Stripf, M. Shafique, W. Ahmed, J. Becker, J. Henkel, “KAHRISMA: A Novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array Architecture”, IEEE/ACM 13th Design Automation and Test in Europe Conference (DATE’10), Dresden, Germany, pp. 819-824, March 2010.
  • M. Shafique, L. Bauer, J. Henkel, “enBudget: A Run-Time Adaptive Predictive Energy-Budgeting Scheme for Energy-Aware Motion Estimation in H.264/MPEG-4 AVC Video Encoder”, IEEE/ACM 13th Design Automation and Test in Europe Conference (DATE’10), Dresden, Germany, pp. 1725-1730, March 2010.
  • M. Shafique, L. Bauer, J. Henkel, “REMiS: Run-time Energy Minimization Scheme in a Reconfigurable Processor with Dynamic Power-Gated Instruction Set”, IEEE/ACM 27th International Conference on Computer-Aided Design (ICCAD’09), San Jose, California, USA, pp. 55-62, November 2009.
  • L. Bauer, M. Shafique, J. Henkel, “MinDeg: A Performance-guided Replacement Policy for Run-time Reconfigurable Accelerators”, IEEE International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS’09), Grenoble, France, pp. 335-342, October 2009.
  • L. Bauer, M. Shafique, J. Henkel, “Cross-Architectural Design Space Exploration Tool for Reconfigurable Processors”, IEEE/ACM 12th Design Automation and Test in Europe Conference (DATE’09), Nice, France, pp. 958-963, April 2009.
  • M. Shafique, L. Bauer, J. Henkel, “A Parallel Approach for High Performance Hardware Design of Intra Prediction in H.264/AVC Video Codec”, IEEE/ACM 12th Design Automation and Test in Europe Conference (DATE’09), Nice, France, pp. 1434-1439, April 2009.
  • L. Bauer, M. Shafique, J. Henkel, “A Computation- and Communication-Infrastructure for Modular Special Instructions in a Dynamically Reconfigurable Processor”, IEEE 18th International Conference on Field Programmable Logic and Applications (FPL’08), Heidelberg, Germany, pp. 203-208, September 2008.
  • M. Shafique, L. Bauer, J. Henkel, “3-Tier Dynamically Adaptive Power-Aware Motion Estimator for H.264/AVC Video Encoding”, ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED’08), Bangalore, India, pp. 147-152, August 2008.
  • L. Bauer, M. Shafique, J. Henkel, “Run-time Instruction Set Selection in a Transmutable Embedded Processor”, ACM/IEEE/EDA 45th Design Automation Conference (DAC’08), Anaheim, CA, USA, pp. 56-61, June 2008.
    Received a “European Network of Excellence on High Performance and Embedded Architecture and Compilation” HiPEAC Paper Award.
  • L. Bauer, M. Shafique, S. Kreutz, J. Henkel, “Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set”, IEEE/ACM 11th Design Automation and Test in Europe Conference (DATE’08), Munich, Germany, pp. 752-757, March 2008.
    Received the DATE´08 Best Paper Award.
  • L. Bauer, M. Shafique, D. Teufel, J. Henkel, “A Self-Adaptive Extensible Embedded Processor”, IEEE/ACM First International Conference on Self-Adaptive and Self-Organizing Systems (SASO’07), Boston, MA, USA, pp. 344-347, July 2007.
  • L. Bauer, M. Shafique, S. Kramer, J. Henkel, “RISPP: Rotating Instruction Set Processing Platform”, ACM/IEEE/EDA 44th Design Automation Conference (DAC’07), San Diego, CA, USA, pp. 791-796, June 2007.

 

 

Workshops

  • Benjamin Oechslein, Jens Schedel, Jürgen Kleinöder, Lars Bauer, Jörg Henkel, Daniel Lohmann, Wolfgang Schröder-Preikschat, “OctoPOS: A Parallel Operating System for Invasive Computing”, Systems for Future Multi-Core Architectures (SFMA’11), Salzburg, Austria, April 2011.
  • M. Shafique, L. Bauer, J. Henkel, “Optimized Application Architecture of the H.264 Video Encoder for Application Specific Platforms”, 5th IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia’07), Salzburg, Austria, pp. 119-124, October 2007.
  • L. Bauer, M. Shafique, J. Henkel, “Efficient Resource Utilization for an Extensible Processor through Dynamic Instruction Set Adaptation”, 5th Workshop on Application Specific Processors (WASP’07), Salzburg, Austria, pp. 39-46, October 2007.

CV Lars Bauer

Short CV

2011 – present         Head of the KIT Young Investigator Group (YIG) “Methods and Architectures for emerging dynamically reconfigurable systems”.

2009 – present         Research Assistant, Lecturer, and Group Leader at the Chair for Embedded Systems, Computer Science Department, Karlsruhe Institute of Technology (KIT), Germany.

2009                           Doctorate (Dr.-Ing., Summa cum Laude) at the Computer Science Department, University of Karlsruhe (TH). Thesis: “RISPP: A Run-time Adaptive Reconfigurable Embedded Processor” (Supervisor: Prof. Dr.-Ing. Jörg Henkel).

2004 – 2009             Doctoral Researcher at the Chair for Embedded Systems (Prof. Dr.-Ing. Jörg Henkel), Computer Science Department, University of Karlsruhe (TH).

2004                           Graduation (Dipl.-Inform., Magna cum Laude) at the University of Karlsruhe (TH).

2000 – 2002             Student Assistant (HiWi) at the Computer Science Department, University of Karlsruhe (TH).

1998 – 2004             Computer Science student at the University of Karlsruhe (TH) with majors in Embedded Systems, Electrical Engineering, and Software Engineering/Compiler Construction.

 

 

Awards

  • Promotion as Young Investigator within the Excellence Initiative of the KIT with 80,000 Euro per year over the next 4 years (2011-2015; altogether 320,000 Euro).
  • EDAA Outstanding Dissertations Award (prize money EUR 1,000) of the European Design and Automation Association (EDAA) for “New directions in embedded system design and embedded software”.
  • Outstanding Dissertation Award (prize money EUR 1,500) of the ‘Foerderverein des Forschungszentrum Informatik (FZI)’ (Research Center for Information Technologies), Karlsruhe, Germany.
  • MaXentric Technologies AHS 2011 Best Paper Award for the paper “Concepts, Architectures, and Run-time Systems for Efficient and Adaptive Reconfigurable Processors”.
  • IEEE/ACM William J. McCalla ICCAD 2010 Best Paper Candidate for the paper “Selective Instruction Set Muting for Energy-Aware Adaptive Processors”.
  • Ph.D. was distinguished as “Summa cum Laude”.
  • Design Automation and Test in Europe Conference (DATE 2008) Best Paper Award for the paper “Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set”.
  • European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC) Paper Award for the DAC 2008 paper “Run-time Instruction Set Selection in a Transmutable Embedded Processor”.

 

Services

  • SIES 2012 (7th IEEE International Symposium on Industrial Embedded Systems): co-Chair of the work-in-progress session
  • CODES+ISSS 2011 (International Conference on Hardware/Software Codesign and System Synthesis): Technical Program Committee member
  • ESWeek 2011 (Embedded Systems Week): Publicity Chair
  • ESTIMedia 2011 (9th IEEE Symposium on Embedded Systems for Real-time Multimedia): Technical Program Committee member
  • RTAS 2011 (17th IEEE Real-Time and Embedded Technology and Applications Symposium): Technical Program Committee member
  • PARMA 2011 (2nd Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures: Technical Program Committee member
  • CPSNA 2011 (1st International Workshop on Cyber-Physical Systems, Networks, and Applications): Technical Program Committee member
  • CODES+ISSS 2010 (International Conference on Hardware/Software Codesign and System Synthesis): Technical Program Committee member
  • Reviewer for many international Journals and Conferences, e.g. Transactions on Very Large Scale Integration Systems (TVLSI), Transactions on Design Automation of Electronic Systems (TODAES), Transactions in Embedded Computing Systems (TECS), International Journal of Reconfigurable Computing (IJRC), Design Automation Conference (DAC), International Conference on Computer-Aided Design (ICCAD), Asia and South Pacific Design Automation Conference (ASP-DAC), International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), International Conference on Compilers, Architecture, and Synthesis (CASES), ISLPED, SiPS, SASP, SCOPES, ISVLSI, ARCS, RSP, IC-SAMOS.

 

 

Projects from Third-Party Funding

  • “Methods and Architectures for emerging dynamically reconfigurable systems”, 4-year project (2011-2015), funded by the Karlsruhe Institute of Technology (KIT) as a Young Investigator Group (YIG) with 80,000 Euro (approximately 1.5 research positions) per year, altogether 320,000 Euro.
                                                                                                                                                         Role: Principal Investigator
  • “Adaptive Application-Specific Invasive Microarchitectures”, 4-year project (2010-2014) within the SFB-TR 89 “Invasive Computing”, funded by Deutsche Forschungsgemeinschaft (DFG); our part: 1 research position.
                                                                                                                                                         Role: Principal Investigator
  • Invasive Run-Time Support System (iRTSS)”, 4-year project (2010-2014) within the SFB-TR 89 “Invasive Computing”, funded by Deutsche Forschungsgemeinschaft (DFG); our part: 1 research position.
                                                                                                                                                         Role: Principal Investigator
  • “OTERA: Online Test Strategies for Reliable Reconfigurable Architectures”, 2-year project (2010-2012) within the SPP 1500 “Design and Architectures of Dependable Embedded Systems – A Grand Challenge in the Nano Age”, funded by Deutsche Forschungsgemeinschaft (DFG); our part: 1 research position.
                                                                                                              Role: Contribution to writing proposal and research
  • Industrial project in the automotive domain, 1.5-year project (2010-2011) funded by Bundesministerium für Wirtschaft und Technologie (BMWi); our part: 2 research positions.
                                                                                                              Role: Contribution to writing proposal and research
  • “KAHRISMA (KArlsruhe’s Hyper­morphic Reconfigurable-Instruction-Set Multi-grained-Array) Architecture”, 3-year project (2009-2012) funded by Deutsche Forschungsgemeinschaft (DFG); our part: 1 research position.
                                                                                                              Role: Contribution to writing proposal and research
  • “DodOrg: Stability and Robustness”, 2-year project (2009-2011) within the SPP 1183 “Organic Computing”, funded by Deutsche Forschungsgemeinschaft (DFG); our part: 1 research position.
                                                                                                                                      Role: Contribution to writing proposal
  • “DodOrg: Plasticity, Dynamics, and Stability”, 1-year project (2008-2009) within the SPP 1183 “Organic Computing”, funded by Deutsche Forschungsgemeinschaft (DFG); our part: 1 research position.
                                                                                                                                      Role: Contribution to writing proposal

 

 

Invited Talks

  • “Adaptive Reconfigurable Instruction Set Processors”, GI/ITG Workshop on ‘Reconfigurable Systems: Architectures, Tools, Applications’, Darmstadt, Germany, April 2011.
  • “Automatic extraction and selection of complex modular Special Instructions for reconfigurable processor architectures”, Intel Workshop on ‘Approaches and tools for efficient design of SoCs’, St. Petersburg, Russia, November 2010.
  • “Run-time Adaptation for Reconfigurable Embedded Processors”, Dagstuhl Seminar on ‘Dynamically Reconfigurable Architectures’, Schloss Dagstuhl - Leibniz Center for Informatics, Germany, July 2010.
  • “KAHRISMA: A Multi-grained Reconfigurable Multicore Architecture”, 10th International Forum on Embedded MPSoC and Multicore (MPSoC´10), Gifu city, Gifu, Japan, June/July 2010.
  • “RISPP: Rotating Instruction Set Processing Platform”, Colloquium of the DFG Priority Program 1148 ‘Rekonfigurierbare Rechensysteme’ (Reconfigurable Computing Systems) (SPP-RR), Karlsruhe, Germany, September 2009.
  • “Classifying and Evaluating Performance-relevant Parameters for Reconfigurable Processors”, 9th International Forum on Embedded MPSoC and Multicore (MPSoC´09), Savannah, GA, USA, August 2009.